Fwd: Keith's Image Stacker For Mac

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Fwd: Keith's Image Stacker For Mac Average ratng: 5,8/10 8880 reviews

Oct 04, 2003  Keith's Image Stacker can use Quicktime files, but I can't figure out how to use Keith's properly. So, I use QuickTime Pro to convert the.mov files to AVIs (so I can use in Registax on my Windows machine), but once I get a decent result by changing compression settings, I end up with AVIs that are about 800 megabytes! Some of the best Mac Astronomy and Astrophotography software available today. Planning & Observation. Keith's Image Stacker. Planetary Imager. Observatory Astronomy Image Catalog Application for the Mac. Apr 30, 2018. I’m looking for a stacker that will run on Mac and provide the power and results of RegiStax. I have looked at Keiths Image Stacker but it does not seem to be very user friendly. I have used Lynkeos, but it does not seem to be as powerful as RegiStax.

IEEE 1588v2 is a standard that defines a Precision Time Protocol (PTP) used in packet networking to precisely synchronize the real Time-of-Day (ToD) clocks and frequency sources in a distributed system to a master ToD clock, which is synchronized to a global clock source. Traditionally, such synchronization has been achieved in TDM (Time Division Multiplexing) networks due to their control on timing with their precise frequency and clocking hierarchy. However, with the advent of 1588v2, synchronization to nanosecond precision has become a possibility within packet networks, enabling low-cost phase and frequency synchronization in applications such as wireless, mobile backhaul, wireline and industrial instrumentation potentially replacing the higher cost of TDM networks. The following diagram illustrates the 1588 system solution using Altera developed Ethernet driver and PTP stack running on top of Altera SoC, Ethernet MAC and transceiver with 1588 capability IPs. The software stack also provides accessibility to control and status registers for configuration using Ethtool and accessibility to the MAC statistic counters to observe the system performance using iperf utility. Though the complete solution can be implemented in software, the hardware assisted the system to achieve the high accuracy needed in some applications such as mobile backhaul. All Altera Ethernet MAC and PHY 1588 hardware solution supports a static error of +/- 3ns for throughputs of 10Gbps with random error of +/- 1ns from the PHY.

The following describe the different PTP clocks present in the PTP protocol:. Ordinary Clock: An ordinary clock (OC) device can be either a master clock or a slave clock and it is a single port in a 1588 clock domain network.

Transparent Clock: A transparent clock (TC) device updates the PTP messages with the time taken by them to traverse through the network device from an ingress Ethernet port to an egress Ethernet port. In other words, the TC device updates the PTP event messages with their residence delay in the devices before the messages are transmitted out. The TC has two modes; end-to-end mode and peer-to-peer mode. The end-to-end TC uses the end-to-end delay measurement mechanism between slave clocks and the master clock. The peer-to-peer TC involves link delay correction using peer-to-peer delay measurement mechanism, in addition to the residence delay correction. Boundary Clock: A boundary clock (BC) device has multiple ports in a 1588 clock domain with one slave clock port and possibly more than one master clock port.

The BC maintains the same timescale for the slave clock port and possibly multiple master clock ports. A BC helps to avoid the long chain of transparent clocks between the network 1588 grandmaster and slave, leading to higher inaccuracy in the slave’s ToD synchronization. The BC also helps to divide a larger 1588 network, thus reducing the traffic going all the way back to the original 1588 master. Typical application BC devices include routers, gateways and bridges.

Precision Time Protocol (PTP) Synchronization Process. The synchronization process involves ToD (Time of Day) offset correction and frequency correction between a master clock and a slave clock. The slave clock collects necessary data to synchronize its clock with master’s clock through event messages. Below is the synchronization process flow:. The slave collects the timestamps of T1, T2, T3 and T4 through the event messages; Sync, DelayReq, and DelayResp and calculates the mean path delay (MPD). At the next sync message, the slave calculates the ToD offset by subtracting the MPD from the result of T6-T5 and adjusts its ToD counter accordingly.

The BC device is used to break the long chain of TC nodes and maintain the accuracy of the synchronization. The BC device has a slave clock port synchronizing to a master clock external to the BC system. The master ports in a BC system use the timescale maintained by the slave clock within the same BC system. Altera Ethernet MAC and transceiver IPs with fractional arithmetic capability can provide highest accuracy of 6.99ns for Ethernet link of 10Gbps speed, facilitating synchronization required even for stringent applications such as telecom and mobile backhaul.

Further, the design facilitates visual demonstration of the achieved synchronization through PPS (pulse per second) output. The efficacy of the synchronization between the master and slave clock can be observe through the PPS output in an oscilloscope. Functional Flow For A 1588 Ordinary Clock Master/Slave Mode System.

The CPU acting as an OC-master sends a Sync packet to the network via its user logic. The packet parser block extracts the fingerprint (an ID for the PTP packet) after decoding the PTP packet and sends the fingerprint to MAC Tx along with the packet. For 1-step mechanism, the 1588 logic generates a timestamp T1 for the Sync packet before sending it to the PHY. This reference design provides the option to enable timestamping for every packet to integrate with LinuxPTP. However, the design can be changed to only timestamp PTP packets. For 2-step mechanism, the transmitting MAC generates the timestamp T1 before sending the Sync packet to the PHY and stores the timestamp T1 along with its fingerprint in the FIFO.

The OC-master checks if there is a valid entry in the FIFO via interrupt or polling mechanism. It then reads the entry from the FIFO to collect the timestamp T1 and the fingerprint. The dotted arrows in OC-master indicate the blocks involved in 2-step mechanism. The CPU then sends a Follow-up message with timestamp T1, which refers to the Sync packet sent in step 1.

The FPGA hosting the OC-slave clock receives the Sync packet and the receiving MAC generates the timestamp T2. The packet parser stores the corresponding timestamp T2 and the fingerprint in the FIFO. You can design a packet parser which can validates the incoming packet as a PTP packet and stores the timestamp T2 along with its fingerprint in the RX FIFO, ignoring the timestamps for the non-PTP packets. The CPU receives the Sync packet via user logic and collects timestamp T1 from the received packet. In 2-step mechanism, the CPU acting as the OC-slave collects timestamp T1 from the Follow-up message sent in step 6. The CPU then reads the FIFO to collect the fingerprint and the timestamp T2. The CPU acting as the OC-slave sends DelayReq packet via its user logic.

The packet parser block after decoding the PTP packet extracts the fingerprint and sends it to the MAC block along with the packet. The MAC Tx of the OC-slave clock generates timestamp T3 before sending the packet to the PHY and stores the timestamp along with its fingerprint in the FIFO. The CPU acting as the OC-slave reads the FIFO to obtain the timestamp T3.

The FPGA hosting the OC-master clock receives the DelayReq packet and the receiving MAC generates the timestamp T4. The packet parser stores the corresponding timestamp T4 and the fingerprint in the FIFO. The CPU acting as the OC-master receives the PTP packet via user logic and reads the FIFO to collect the fingerprint and timestamp T4. Next, the CPU sends a DelayResponse packet containing timestamp T4 via its user logic.

The MAC Tx of the OC-master timestamps the DelayResponse packet but the software stack will ignore the timestamp. You can design a packet parser to instruct the MAC to not generate a timestamp for the DelayResponse packet, which already contain the timestamp T4, after decoding the PTP packet. The MAC Tx of the OC-master sends the DelayResponse packet as it is. The FPGA hosting the OC-slave clock receives the DelayResponse packet. The receiving MAC timestamps the DelayResponse packet and stores it in the FIFO. The CPU reads the FIFO but the timestamp collected through the FIFO read is ignored by the software stack.

You can design a packet parser block which able to identify DelayResponse packet type and sends the packet further to the user logic ignoring its timestamp. The CPU receives DelayResponse packet via user logic and collects the timestamp T4 from the packet.

At this point, the stack in the OC-slave has all the timestamps T1, T2, T3, & T4 from which the mean path delay (MPD) is calculated. The OC-slave collects the timestamps T5 & T6 after receiving the next Sync packet, and calculates the ToD offset as described in. Next, with the time difference between two successive Sync packets, the stack in the OC-slave calculates the frequency offset as described in. The stack residing in the OC-slave CPU supplies the calculated ToD offset and frequency offset to Servo algorithm, which can either adjust the PLL settings supplying the PTP clock to the ToD or program the registers in the 1588 IP to synchronize the slave’s ToD with master’s ToD. Step 1 to step 24 is repeated continuously to adjust the settings for slave’s ToD with the calculated ToD and frequency offset. The PPS pulse outputs from the OC-master and the OC-slave can be observed in an oscilloscope to appreciate the efficacy of synchronization process.

The correction field in the PTP header may be updated in any of the above mentioned PTP packets for any fractional arithmetic residue or asymmetry. PTP packet enters the FPGA through cable A and the Mac RX 1588 logic generates timestamp Ti1. The packet parser validates the PTP packet before sending it to the user logic along with the timestamp information, ignoring all timestamps for non-PTP packets. The user logic at the egress port send the PTP packet along with timestamp Ti1 to the packet parser of the egress port. The packet parser, then validates the PTP packet and send the packet along with the timestamp Ti1 to Mac Tx 1588 logic along with the required command.

Mac Tx 1588 logic generates timestamp Te1 and updates the correction factor (CF) in the packet header. The CF field contains the new residence delay, calculated as CF' = CF + Te1-Ti1. The PHY, then transmits the PTP packet to the network. The same flow from step 1 to step 6 applies to the PTP packet received by cable B, with the timestamp components of Ti2 and Te2.

For 2-step mechanism, the CPU collects the ingress and egress timestamps from FIFOs, but the PTP packet remain unchanged. The ingress port receives a follow-up packet from the network and Mac Rx 1588 logic generates a timestamp for the follow-up packet. The packet parser verifies it is a follow-up packet and send it to the CPU via user logic. The CPU updates the follow-up packet after matching the packet's fingerprints with the new correction field of CF'=CF + Te - Ti before sending it to the egress port. The function of a boundary clock mode system is to terminate a long chain of transparent clocks leading to high inaccuracy, and maintain a single timescale.

A boundary clock commonly contains a slave clock port and at least one master clock port. However, the boundary clock has all the ports in one domain and maintain the timescale used in the domain. The following figure illustrates a BC mode system consists of one slave port and two master ports. The BC-slave port synchronizes with an external grand master clock through the network.

The BC-master ports synchronizes its clocks with the BC-slave port. In the figure, one ToD module is connected to the BC-slave port and the BC-master ports.

Each of the ports shown in the figure operates independently. Timestamp T1 and T2 are synchronized to an external grand master clock while timestamp T3 and T4 are synchronizes to the BC-slave ToD. The CPU hosts the independent stacks for the BC-slave port and the two BC-master ports with the common timescale of the BC-slave ToD. Timestamp Functional Flow for BC Slave Port:. The receiving MAC of the BC-slave port receives a Sync packet with timestamp T1 from external 1588 system through cable A and generates timestamp T2. A packet parser validates the incoming packet and stores timestamp T2 and its fingerprint in the FIFO. The CPU receives the Sync packet with timestamp T1 via user logic.

In 2-step mechanism, the receiving MAC of BC-slave port receives a Follow-Up message timestamp T1 which refers to the Sync message in step 1. The CPU then reads the FIFO to collect the fingerprint and the timestamp T2. The CPU sends DelayReq packet via its user logic. The packet parser block after decoding the PTP packet extracts the fingerprint and sends it to the MAC block along with the packet. The MAC Tx of the BC-slave generates timestamp T3 before sending the packet to the PHY and stores the timestamp along with its fingerprint in the FIFO.

The CPU then reads the FIFO and collects fingerprint and timestamp T3. The receiving MAC receives a DelayResponse packet and timestamp the packet. The MAC then stores the timestamp in the FIFO and forward the DelayResponse packet to packet parser. The packet parser validates the packet and extracts the fingerprint before storing it in the FIFO.

The CPU receives the DelayResponse packet with timestamp T4. The CPU then reads the FIFO but the timestamp collected through the FIFO read is ignored by the software stack. Timestamp Functional Flow for BC Master Port:. The CPU sends a Sync packet to the external 1588 system through MAC Tx and the PHY. The packet parser block extracts the fingerprint after decoding the Sync packet and sends the fingerprint to the MAC Tx along with the packet.

The MAC Tx generates timestamp T5 for the Sync packet before sending it to the PHY. The MAC Tx then stores the timestamp T5 with its fingerprint in the FIFO. The CPU then reads the FIFO to collect the fingerprint and the timestamp T5. For 2-step mechanism, the CPU sends a Follow-up message with timestamp T5 referring to the Sync packet sent in step 1. The receiving MAC of the BC-master clock receives a PDelayReq from external 1588 system through the PHY.

The MAC Rx receives the PDelayReq packet and generates timestamp T6 before storing it in the FIFO. It then sends the PDelayReq to the packet parser. The packet parser decodes the packet and extracts its fingerprint before storing in the FIFO. The CPU receives the PDelayReq packet via user logic and collects the fingerprint and the timestamp T6 from the FIFO. The CPU sends a PDelayResp packet containing the timestamp T6 to the packet parser. The packet parser validates and extracts the PDelayResp packet fingerprint before sending it to the MAC. The MAC Tx receives the packet and generates a timestamp before storing the timestamp and its fingerprint into the FIFO for CPU to read.

However, this timestamp is ignore by the software stack. The MAC Tx then sends the PDelayResp packet as it is. For 2-step mechanism, the CPU reads the entry from the FIFO to collect the timestamp T6 and its fingerprint.

The CPU then sends a PdelayRespFollowUp packet with timestamp T6 to the external 1588 system. This section describes the timestamp packet flow between Linux driver and the system hardware. The reference design uses TX Ingress Timestamp FIFO and RX Ingress Timestamp FIFO to store the timestamp with fingerprint. The Linux PTP driver will access these FIFO to obtain the timestamp information for PTP software processing.

A FIFO status read can be omitted if the FIFO read delay is determined. CPU can read the RX FIFO without any delay while for TX FIFO, a delay is necessary and most often depends on the sum of MTU delay of a scheduled packet, DMA delays and the PTP packet transmit delays. In general, 3.MTU delay is the common value for TX FIFO read delay. Download and install Quartus II Subscription Edition software v14.1 and Altera Arria V SoC Development Kit Installations on your Windows host. Place two Arria V SoC development boards (5ASTFD5K3F40I3NES) side by side. In the following steps, the two Arria V SoC development boards will be referred to as Board A and Board B.

Setup the SMA connections between these 2 boards per below:. Port J24 on Board A connects to port J31 on Board B. Port J25 on Board A connects to port J32 on Board B. Port J24 on Board B connects to port J31 on Board A. Port J25 on Board B connects to port J32 on Board A.

Connect the micro SD card with the bootable image to J5 port on board A. Connect USB II blaster cable from Board A to your Windows host that has Arria V SoC development kit installed.

Turn on the power for Board A to load the bootable image. The Arria V 10GbE appears on the LCD screen on the board when the image is successfully loaded. Open the Clock Control application from the Arria V SoC development kit installation on your Windows host. Set Channel 0 reference clock source, Si570(X3) to 644.53125MHz.

This step is required to run the reference design at 10Gbps data rate. FPGA LED 0 will blink every 2 seconds to indicate that the hardware clock is running at 10Gbps data rate if the reference clock source Si570 is successfully configured. Use ethtool -d eth0 to view MAC register settings. You can use the Ptp4l software in the LinuxPTP package to measure the timestamp accuracy of the reference design. By default, the hardware timestamping is selected and time interval between SYNC messages is set to 1 second. Use testptp -c to view the PTP hardware clock capabilities on both boards. Use ethtool -C eth0 tx-frames 1 command to send packet to the stack without any delay on both boards.

This must be done before executing ptp4l command. Type ptp4l -i eth0 -m to start a PTP Master on Board A with the IP address of 10.0.0.1. Type ptp4l -i eth0 -m -s to start a PTP Client on Board B with the IP address of 10.0.0.2. The PTP measurement starts at this point. Stop the PTP measurement on Board B (PTP client) by pressing CTRL + C on your keyboard.

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Type testptp -f 0 to reset the MAC clock period default to 6.4ns on Board B (PTP client) after the measurement has stopped. Optionally, type testptp -s to reset PTP hardware clock time to system time at PTP client. By default, the PTP Master sends 1 SYNC message per every second.

You can create a configuration file to override the default settings of ptp4l. The following code shows the example of ptp4l configuration file to set PTP Master to send 512 SYNC messages every second. This setting provides a timestamp accuracy of 6.99ns for every 100 samples.

At times, you may need to modify the reference design according to your system requirements and recompile the reference design. You are required to regenerate the alteraeth10g1588refdesignmsgdmatop.qsys file for compilation. Following are the steps to guide you in regenerating the design files and replacing the RBF file into the system image. You are required to use Quartus II Subscription Edition v14.1 for these procedures. Download the alteth1588rd.qsys.zip file to your computer and unzip the folder. Launch Quartus II software. In Quartus II software, click File - Open Project and browse to av1588top.qpf file to open the reference design project.

Once the the project file is open, click on Tools - Qsys in the Quartus II software. In the Qsys interface, click File - Open and browse to alteraeth10g1588refdesignmsgdmatop.qsys file to open the reference design Qsys file. Once the reference design Qsys file is opened, click Generate HDL. Below are the modules available in the Altera 1588 system solution reference design:. A 1588 capable Ethernet MAC and PHY, capable of very precise time stamping of packets with ToD value and an indication on the time-stamp offset. This time stamping achieves equal accuracy in both 1-step and 2-step operations. A ToD clock module that supports loading of real ToD value and fine-grain update of its value and frequency.

Clear-text packet parser that can be used to detect PTP packet types and then tell the Ethernet MAC the time-field offset for the following packet types: UDP over IPv4, UDP over IPv6, stacked VLAN. This block is made available in clear-text so that the user can easily augment the code to cover other packet types the users may need such as MPLS or MAC-in-MAC. ToD synchronizer to synchronize different ToDs running in different clock domains; for example, in a system of network line cards to a system master ToD. These building blocks can be put together in a useful system combined with the user provided CPU and software stack to create a high-quality 1588 solution. It is the responsibility of the software stack, which the user either creates or obtains from a third-party, to implement the overall 1588 stack, including the corresponding logic to support different modes for synchronization process.

The following diagram illustrates the hardware modules in this 1588 system reference design. Altera provides a Time of Day Clock (ToD) module to ease user's implementation when using Altera Ethernet MAC-based 1588 system.

The ToD module is a counter responsible for generating the current real time of day locally. A processor with a Timing Servo Control Software updates the ToD counter, typically via fine-grain adjustments in terms of phase and frequency corrections through relevant registers. The ToD can provide both a 64-bit time useful for the correction field used in a transparent clock (TC) and a full 96-bit time useful for ordinary clock (OC) and boundary clock (BC). You can instantiate a master ToD module to time-stamp the transmitted and received packets.

One ToD module can be shared across multiple MACs. You must enable the 64-bit timestamp when using TC, otherwise use 96-bit timestamp.You may use Altera Ethernet IEEE 1588 TOD Synchronizer to synchronize multiple slave ToDs to a single master ToD. Packet Parser. The Ethernet Packet Classifier functions as a packet parser module for Altera Ethernet MAC-based 1588 system. In the transmit direction, the Packet Parser module is used to determine the type of packet being sent, determine the appropriate location for the time stamp field and provide this information via a command to the 1588 MAC transmitter for further processing. The module is also able to provide the information of the timestamp offset and whether there is an update to the IPv6 UDP correction field.

In the receive direction, this block checks whether the local timestamp of the packet received on the Ethernet MAC receiver is indeed for a PTP packet. For example, the 1588 PTP packet’s timestamp field location relative to the Start Of Packet (SOP) is different for a PTP packet encapsulated over Ethernet versus for a PTP packet encapsulated over UDP over IPv6 over Ethernet. The Central Processing Unit (CPU). A FIFO is used to associate a PTP event with a timestamp for later retrieval. For example, in a 2-step operation, the FIFO will be used to remember the time that a packet has gone out so that it can be looked up and retrieved at the time that the CPU is ready to send out the follow-up response. Though the 1588 protocol is a slow protocol with 128 frames per second, the 1588 packets may arrive in burst or many contexts such as simultaneous flows or many PTP domains can coexist in a single clock device.

Hence, a FIFO is sometimes required depending on the system performance requirements in a 2-step operation. Similarly, in 1-step operation, the timestamp T3 and optionally T2 needs to be collected by the PTP stack through a FIFO. The use cases are an Ordinary Clock-Master in 2-step, Boundary Clock-Master in 2-step, Ordinary Clock-Slave in both 1-step and 2-step, Boundary Clock-Slave in both 1-step and 2-step & Transparent Clock (TC) in 2-step. A typical size of the FIFO required is a network parameter, which can approximately range from 64 to 256 entrees.

The FIFO stores the timestamp along with the signature of the packet for the CPU to read the timestamp later. The CPU can match the timestamp’s signature with its signature of the packet before accepting the timestamp. If the timestamp is read out of order, the CPU can keep a shadow copy of the entry to match with other signatures and read the FIFO for the packet in context.

A FIFO works more efficiently than a CAM the timestamps are read in order. Clocking and Reset Scheme.

PMA Registers Byte Offset Bit R/W Name 0x0088 RO pmatxpllislocked 0x0110 1 RW resettxdigital 2 RW resetrxanalog 3 RW resetrxdigital 0x0184 RW physerialloopback 0x0190 RW pmarxsetlocktodata 0x0194 RW pmarxsetlocktoref 0x0198 RO pmarxislockedtodata 0x019C RO pmarxislockedtoref 0x02A0 0 RW txinvpolarity 1 RW rxinvpolarity 2 RW rxbitreversalenable 3 RW rxbytereversalenable 4 RW forceelectricalidle 0x02A4 0 R rxsyncstatus 1 R rxpatterndetect 2 R rxrlv 3 R rxrmfifodatainserted 4 R rxrmfifodatadeleted 5 R rxdisperr 6 R rxerrdetect. Register Description and Address Offset for PTP Control Module Word Offset Bits Name Type Reset Value Description 0x00 1:0 txrxpktparserclockmode RW 2'b00 Specify the operating clock mode for PTP port. 2'b00: Ordinary Clock 2'b01: Boundary Clock 2'b10: End-to-end Transparent Clock 2'b11: Peer-to-peer Transparent Clock 8 txpktparsertwostepmode RW 1'b0 Specify the operation mode for the synchronization process. 1'b0: 1-step operation mode 1'b1: 2-step operation mode. 10 txpktparserpacketwithcrc RW 1'b0 Enable the packet parser to indicate whether the incoming packet to the MAC includes CRC. This register is required by TX packet parser to calculate the offset location for checksum corrector for UDP/IPv6 packets. 0x04 0 rxpktfltfwduserucastmatch RW 1'b0 Forward unicast packet that matched the MAC address to user logic.

1'b0: Allow unicast packet which matched the MAC address to be forwarded to user logic. 1'b1: Drop unicast packet that matched the MAC address. 1 rxpktfltfwduserucastxmatch RW 1'b1 Forward unicast packet that does not matched the MAC address to user logic.

1'b0: Drop unicast packet that do not match the MAC address. 1'b1: Allow unicast packet which does not match the MAC address to be forwarded to user logic. 2 rxpktfltfwdusermcast RW 1'b1 Forward multicast packet to user logic. 1'b0: Drop multicast packet.

1'b1: Allow multicast packet to be forwarded to user logic. 3 rxpktfltfwduserbcast RW 1'b1 Forward Broadcast packet to user logic. 1'b0: Drop broadcast packet. 1'b1: Allow broadcast packet to be forwarded to user logic. 8 rxpktfltfwdswucastmatch RW 1'b1 Forward unicast packet that matched the MAC address to software. 9 rxpktfltfwdswucastxmatch RW 1'b0 Forward unicast packet that does not matched the MAC address to software. 10 rxpktfltfwdswmcast RW 1'b1 Forward multicast packet to software.

11 rxpktfltfwdswbcast RW 1'b1 Forward Broadcast packet to software. 0x05 31:0 rxpktfltmacaddrprim31to0 RW 32'h0. 6-byte primary MAC address. You must map the address to the registers in the following manner:.

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rxpktfltmacaddrprim31to0 = Last four bytes of the address. rxpktfltmacaddrprim47to32: First two bytes of the address 0x06 15:0 rxpktfltmacaddrprim47to32 RW 16'h0 0x20 0 txfifoclr RW 1'b0 Reset TX Egress TimeStamp FIFO.

1'b0: De-assert reset. 1'b1: Assert reset. 0x21 0 txfifotsfprintrdy RO 1'b0 Indicates the availability of the timestamp and the fingerprint. 1'b0: No timestamp and fingerprint available in the TX Egress Timsestamp FIFO. 1'b1: Timestamp and fingerprint available in the TX Egress Timestamp FIFO.

16:8 txfifousedwords RO 9'b0 Indicates the number of words in the FIFO. 0x25 31:0 txfiforecoveredtstamp31to0 RO 32'h0 The recovered timestamp. For 96-bit timestamp format, all TX FIFO recovered timestamp register-sets are used. For 64-bit timestamp format, only txfiforecoveredtstamp63to32 and txfiforecoveredtstamp31to0 registers are used.

Read to txfiforecoveredtstamp95to64 register indicates the completion of a read transaction for timestamp and fingerprint registers. Altera recommend to follow the below order to read the timestamp and fingerprint registers:. Read txfiforecoveredfprint31to0 register (optional). Read txfiforecoveredtstamp31to0 register. Read txfiforecoveredtstamp63to32 register. Read txfiforecoveredtstamp95to64 register. 0x26 31:0 txfiforecoveredtstamp63to32 RO 32'h0 0x27 31:0 txfiforecoveredtstamp95to64 RO 32'h0 0x28 19:0 txfiforecoveredfprint31to0 RW 20'h0 The fingerprint corresponding to the timestamp.

Read this register if the PTP stack is require to verify the timestamp correspond to the packet. 0x40 0 rxfifoclr RW 1'b0 Reset RX Ingress TimeStamp FIFO. 1'b0: De-assert reset.

1'b1: Assert reset. 0x41 0 rxfifotsfprintrdy RO 1'b0 Indicates the availability of the timestamp and the fingerprint. 1'b0: No timestamp and fingerprint available in the RX Ingres Timestamp FIFO. 1'b1: Timestamp and fingerprint available in the RX Ingress Timestamp FIFO. 16:8 rxfifousedwords RO 9'b0 Indicates the number of words in the FIFO. 0x45 31:0 rxfiforecoveredtstamp31to0 RO 32'h0 The recovered timestamp.

For 96-bit timestamp format, all RX FIFO recovered timestamp register-sets are used. For 64-bit timestamp format, only rxfiforecoveredtstamp63to32 and rxfiforecoveredtstamp31to0 registers are used.

Read to rxfiforecoveredtstamp95to64 register indicates the completion of a read transaction for timestamp and fingerprint registers. Altera recommend to follow the below order to read the timestamp and fingerprint registers:. Read rxfiforecoveredfprint31to0 register (optional). Read rxfiforecoveredtstamp31to0 register. Read rxfiforecoveredtstamp63to32 register. Read Rxfiforecoveredtstamp95to64 register.

0x46 31:0 rxfiforecoveredtstamp63to32 RO 32'h0 0x47 31:0 rxfiforecoveredtstamp95to64 RO 32'h0 0x48 19:0 rxfiforecoveredfprint31to0 RW 20'h0 The fingerprint corresponding to the timestamp. Read this register if the PTP stack is require to verify the timestamp correspond to the packet. 1588 ToD Clock Registers. Register Description and Address Offset for 1588 TOD Clock Byte Offset R/W Name Description HW Reset 0x0000 RW SecondsH. Bits 0 to 15: High-order 16-bit second field. Bits 16 to 31: Not used. 0x0 0x0004 RW SecondsL Bits 0 to 32: Low-order 32-bit second field.

0x0 0x0008 RW NanoSec Bits 0 to 32: 32-bit nanosecond field. 0x0 0x0010 RW Period. Bits 0 to 15: Period in fractional nanosecond.

Bits 16 to 19: Period in nanosecond. Bits 20 to 31: Not used. N 0x0014 RW AdjustPeriod The period for the offset adjustment. Bits 0 to 15: Period in fractional nanosecond. Bits 16 to 19: Period in nanosecond. Bits 20 to 31: Not used.

0x0 0x0018 RW AdjustCount. Bits 0 to 19: The number of AdjustPeriod clock cycles used during offset adjustment.

Bits 20 to 31: Not used. 0x0 0x001C RW DriftAdjust The drift of ToD adjusted periodically by adding a correction value as configured in this register space. Bits 0 to 15: Adjustment value in fractional nanosecond (DRIFTADJUSTFNS). This value is added into the current ToD during the adjustment. Bits 16 to 19: Adjustment value in nanosecond (DRIFTADJUSTNS). This value is added into the current ToD during the adjustment. Bits 20 to 32: Not used.

0x0 0x0020 RW DriftAdjustRate The count of clock cycles for each ToD’s drift adjustment to take effect. Bits 0 to 15: The number of clock cycles (ADJUSTRATE). The ToD adjustment happens once after every period in number of clock cycles as indicated by this register space. Bits 20 to 32: Not used. 0x0 Interface Signals. Clock and Reset Interface Signals Signal Direction Width Description resetresetn input 1 Reset signal for the system reference design.

This is asynchronous and active low signal. Fpgaclk100 input 1 Arria V SoC operating clock. Refclk6440 input 1 Reference clock for Altera 10GBASE-R PHY for channel 0. Refclk6441 input 1 Reference clock for Altera 10GBASE-R PHY for channel 1. Clk644out output 1 Reference clock for Altera 10GBASE-R PHY output signal for debug purposes. PHY Interface Signals.

Arria V HPS Interface Signals Signal Direction Width Description HPS DDR3 SDRAM hpsmemorymema Output 15 Address bus. Hpsmemorymemba Output 3 Bank address. Hpsmemorymemck memckn Output 1 Memory clock. Memcke Output 1 Clock enable. Memcsn Output 1 Chip select.

Memrasn Output 1 Row address strobe. Memcasn Output 1 Column address strobe.

Memwen Output 1 Write enable. Memresetn Output 1 Reset memdq Bidirectional 40 Data. Memdqs Bidirectional 5 Data strobe. Memdqsn Bidirectional 5 Data strobe. Memodt Output 1 On-die termination. Memdm Output 5 Data mask. Octrzqin Input 1 OCT reference resistor pins for RZQ.

HPS Peripheral hpsuart0TX Output 1 Output signal for UART channel 0. This signal is required for serial console communication to host. Hpsuart0RX Input 1 Input signal for UART channel 0. This signal is required for serial console communication to host.

IEEE 1588v2 is a standard that defines a Precision Time Protocol (PTP) used in packet networking to precisely synchronize the real Time-of-Day (ToD) clocks and frequency sources in a distributed system to a master ToD clock, which is synchronized to a global clock source. Traditionally, such synchronization has been achieved in TDM (Time Division Multiplexing) networks due to their control on timing with their precise frequency and clocking hierarchy. However, with the advent of 1588v2, synchronization to nanosecond precision has become a possibility within packet networks, enabling low-cost phase and frequency synchronization in applications such as wireless, mobile backhaul, wireline and industrial instrumentation potentially replacing the higher cost of TDM networks. The following diagram illustrates the 1588 system solution using Altera developed Ethernet driver and PTP stack running on top of Altera SoC, Ethernet MAC and transceiver with 1588 capability IPs.

The software stack also provides accessibility to control and status registers for configuration using Ethtool and accessibility to the MAC statistic counters to observe the system performance using iperf utility. Though the complete solution can be implemented in software, the hardware assisted the system to achieve the high accuracy needed in some applications such as mobile backhaul. All Altera Ethernet MAC and PHY 1588 hardware solution supports a static error of +/- 3ns for throughputs of 10Gbps with random error of +/- 1ns from the PHY. The following describe the different PTP clocks present in the PTP protocol:. Ordinary Clock: An ordinary clock (OC) device can be either a master clock or a slave clock and it is a single port in a 1588 clock domain network. Transparent Clock: A transparent clock (TC) device updates the PTP messages with the time taken by them to traverse through the network device from an ingress Ethernet port to an egress Ethernet port. In other words, the TC device updates the PTP event messages with their residence delay in the devices before the messages are transmitted out.

The TC has two modes; end-to-end mode and peer-to-peer mode. The end-to-end TC uses the end-to-end delay measurement mechanism between slave clocks and the master clock. The peer-to-peer TC involves link delay correction using peer-to-peer delay measurement mechanism, in addition to the residence delay correction.

Boundary Clock: A boundary clock (BC) device has multiple ports in a 1588 clock domain with one slave clock port and possibly more than one master clock port. The BC maintains the same timescale for the slave clock port and possibly multiple master clock ports. A BC helps to avoid the long chain of transparent clocks between the network 1588 grandmaster and slave, leading to higher inaccuracy in the slave’s ToD synchronization. The BC also helps to divide a larger 1588 network, thus reducing the traffic going all the way back to the original 1588 master. Typical application BC devices include routers, gateways and bridges. Precision Time Protocol (PTP) Synchronization Process.

The synchronization process involves ToD (Time of Day) offset correction and frequency correction between a master clock and a slave clock. The slave clock collects necessary data to synchronize its clock with master’s clock through event messages. Below is the synchronization process flow:.

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The slave collects the timestamps of T1, T2, T3 and T4 through the event messages; Sync, DelayReq, and DelayResp and calculates the mean path delay (MPD). At the next sync message, the slave calculates the ToD offset by subtracting the MPD from the result of T6-T5 and adjusts its ToD counter accordingly. The BC device is used to break the long chain of TC nodes and maintain the accuracy of the synchronization. The BC device has a slave clock port synchronizing to a master clock external to the BC system. The master ports in a BC system use the timescale maintained by the slave clock within the same BC system. Altera Ethernet MAC and transceiver IPs with fractional arithmetic capability can provide highest accuracy of 6.99ns for Ethernet link of 10Gbps speed, facilitating synchronization required even for stringent applications such as telecom and mobile backhaul. Further, the design facilitates visual demonstration of the achieved synchronization through PPS (pulse per second) output.

The efficacy of the synchronization between the master and slave clock can be observe through the PPS output in an oscilloscope. Functional Flow For A 1588 Ordinary Clock Master/Slave Mode System. The CPU acting as an OC-master sends a Sync packet to the network via its user logic. The packet parser block extracts the fingerprint (an ID for the PTP packet) after decoding the PTP packet and sends the fingerprint to MAC Tx along with the packet. For 1-step mechanism, the 1588 logic generates a timestamp T1 for the Sync packet before sending it to the PHY. This reference design provides the option to enable timestamping for every packet to integrate with LinuxPTP. However, the design can be changed to only timestamp PTP packets.

For 2-step mechanism, the transmitting MAC generates the timestamp T1 before sending the Sync packet to the PHY and stores the timestamp T1 along with its fingerprint in the FIFO. The OC-master checks if there is a valid entry in the FIFO via interrupt or polling mechanism. It then reads the entry from the FIFO to collect the timestamp T1 and the fingerprint.

The dotted arrows in OC-master indicate the blocks involved in 2-step mechanism. The CPU then sends a Follow-up message with timestamp T1, which refers to the Sync packet sent in step 1. The FPGA hosting the OC-slave clock receives the Sync packet and the receiving MAC generates the timestamp T2. The packet parser stores the corresponding timestamp T2 and the fingerprint in the FIFO. You can design a packet parser which can validates the incoming packet as a PTP packet and stores the timestamp T2 along with its fingerprint in the RX FIFO, ignoring the timestamps for the non-PTP packets.

The CPU receives the Sync packet via user logic and collects timestamp T1 from the received packet. In 2-step mechanism, the CPU acting as the OC-slave collects timestamp T1 from the Follow-up message sent in step 6.

The CPU then reads the FIFO to collect the fingerprint and the timestamp T2. The CPU acting as the OC-slave sends DelayReq packet via its user logic.

The packet parser block after decoding the PTP packet extracts the fingerprint and sends it to the MAC block along with the packet. The MAC Tx of the OC-slave clock generates timestamp T3 before sending the packet to the PHY and stores the timestamp along with its fingerprint in the FIFO.

The CPU acting as the OC-slave reads the FIFO to obtain the timestamp T3. The FPGA hosting the OC-master clock receives the DelayReq packet and the receiving MAC generates the timestamp T4. The packet parser stores the corresponding timestamp T4 and the fingerprint in the FIFO. The CPU acting as the OC-master receives the PTP packet via user logic and reads the FIFO to collect the fingerprint and timestamp T4. Next, the CPU sends a DelayResponse packet containing timestamp T4 via its user logic. The MAC Tx of the OC-master timestamps the DelayResponse packet but the software stack will ignore the timestamp.

You can design a packet parser to instruct the MAC to not generate a timestamp for the DelayResponse packet, which already contain the timestamp T4, after decoding the PTP packet. The MAC Tx of the OC-master sends the DelayResponse packet as it is. The FPGA hosting the OC-slave clock receives the DelayResponse packet.

The receiving MAC timestamps the DelayResponse packet and stores it in the FIFO. The CPU reads the FIFO but the timestamp collected through the FIFO read is ignored by the software stack.

You can design a packet parser block which able to identify DelayResponse packet type and sends the packet further to the user logic ignoring its timestamp. The CPU receives DelayResponse packet via user logic and collects the timestamp T4 from the packet. At this point, the stack in the OC-slave has all the timestamps T1, T2, T3, & T4 from which the mean path delay (MPD) is calculated. The OC-slave collects the timestamps T5 & T6 after receiving the next Sync packet, and calculates the ToD offset as described in. Next, with the time difference between two successive Sync packets, the stack in the OC-slave calculates the frequency offset as described in. The stack residing in the OC-slave CPU supplies the calculated ToD offset and frequency offset to Servo algorithm, which can either adjust the PLL settings supplying the PTP clock to the ToD or program the registers in the 1588 IP to synchronize the slave’s ToD with master’s ToD. Step 1 to step 24 is repeated continuously to adjust the settings for slave’s ToD with the calculated ToD and frequency offset.

The PPS pulse outputs from the OC-master and the OC-slave can be observed in an oscilloscope to appreciate the efficacy of synchronization process. The correction field in the PTP header may be updated in any of the above mentioned PTP packets for any fractional arithmetic residue or asymmetry. PTP packet enters the FPGA through cable A and the Mac RX 1588 logic generates timestamp Ti1. The packet parser validates the PTP packet before sending it to the user logic along with the timestamp information, ignoring all timestamps for non-PTP packets.

The user logic at the egress port send the PTP packet along with timestamp Ti1 to the packet parser of the egress port. The packet parser, then validates the PTP packet and send the packet along with the timestamp Ti1 to Mac Tx 1588 logic along with the required command. Mac Tx 1588 logic generates timestamp Te1 and updates the correction factor (CF) in the packet header. The CF field contains the new residence delay, calculated as CF' = CF + Te1-Ti1. The PHY, then transmits the PTP packet to the network. The same flow from step 1 to step 6 applies to the PTP packet received by cable B, with the timestamp components of Ti2 and Te2.

For 2-step mechanism, the CPU collects the ingress and egress timestamps from FIFOs, but the PTP packet remain unchanged. The ingress port receives a follow-up packet from the network and Mac Rx 1588 logic generates a timestamp for the follow-up packet. The packet parser verifies it is a follow-up packet and send it to the CPU via user logic. The CPU updates the follow-up packet after matching the packet's fingerprints with the new correction field of CF'=CF + Te - Ti before sending it to the egress port. The function of a boundary clock mode system is to terminate a long chain of transparent clocks leading to high inaccuracy, and maintain a single timescale. A boundary clock commonly contains a slave clock port and at least one master clock port. However, the boundary clock has all the ports in one domain and maintain the timescale used in the domain.

The following figure illustrates a BC mode system consists of one slave port and two master ports. The BC-slave port synchronizes with an external grand master clock through the network. The BC-master ports synchronizes its clocks with the BC-slave port. In the figure, one ToD module is connected to the BC-slave port and the BC-master ports. Each of the ports shown in the figure operates independently.

Timestamp T1 and T2 are synchronized to an external grand master clock while timestamp T3 and T4 are synchronizes to the BC-slave ToD. The CPU hosts the independent stacks for the BC-slave port and the two BC-master ports with the common timescale of the BC-slave ToD. Timestamp Functional Flow for BC Slave Port:. The receiving MAC of the BC-slave port receives a Sync packet with timestamp T1 from external 1588 system through cable A and generates timestamp T2. A packet parser validates the incoming packet and stores timestamp T2 and its fingerprint in the FIFO. The CPU receives the Sync packet with timestamp T1 via user logic.

In 2-step mechanism, the receiving MAC of BC-slave port receives a Follow-Up message timestamp T1 which refers to the Sync message in step 1. The CPU then reads the FIFO to collect the fingerprint and the timestamp T2. The CPU sends DelayReq packet via its user logic.

The packet parser block after decoding the PTP packet extracts the fingerprint and sends it to the MAC block along with the packet. The MAC Tx of the BC-slave generates timestamp T3 before sending the packet to the PHY and stores the timestamp along with its fingerprint in the FIFO. The CPU then reads the FIFO and collects fingerprint and timestamp T3. The receiving MAC receives a DelayResponse packet and timestamp the packet. The MAC then stores the timestamp in the FIFO and forward the DelayResponse packet to packet parser. The packet parser validates the packet and extracts the fingerprint before storing it in the FIFO.

The CPU receives the DelayResponse packet with timestamp T4. The CPU then reads the FIFO but the timestamp collected through the FIFO read is ignored by the software stack. Timestamp Functional Flow for BC Master Port:. The CPU sends a Sync packet to the external 1588 system through MAC Tx and the PHY. The packet parser block extracts the fingerprint after decoding the Sync packet and sends the fingerprint to the MAC Tx along with the packet. The MAC Tx generates timestamp T5 for the Sync packet before sending it to the PHY. The MAC Tx then stores the timestamp T5 with its fingerprint in the FIFO.

The CPU then reads the FIFO to collect the fingerprint and the timestamp T5. For 2-step mechanism, the CPU sends a Follow-up message with timestamp T5 referring to the Sync packet sent in step 1. The receiving MAC of the BC-master clock receives a PDelayReq from external 1588 system through the PHY. The MAC Rx receives the PDelayReq packet and generates timestamp T6 before storing it in the FIFO. It then sends the PDelayReq to the packet parser.

The packet parser decodes the packet and extracts its fingerprint before storing in the FIFO. The CPU receives the PDelayReq packet via user logic and collects the fingerprint and the timestamp T6 from the FIFO. The CPU sends a PDelayResp packet containing the timestamp T6 to the packet parser. The packet parser validates and extracts the PDelayResp packet fingerprint before sending it to the MAC. The MAC Tx receives the packet and generates a timestamp before storing the timestamp and its fingerprint into the FIFO for CPU to read.

However, this timestamp is ignore by the software stack. The MAC Tx then sends the PDelayResp packet as it is. For 2-step mechanism, the CPU reads the entry from the FIFO to collect the timestamp T6 and its fingerprint. The CPU then sends a PdelayRespFollowUp packet with timestamp T6 to the external 1588 system. This section describes the timestamp packet flow between Linux driver and the system hardware. The reference design uses TX Ingress Timestamp FIFO and RX Ingress Timestamp FIFO to store the timestamp with fingerprint. The Linux PTP driver will access these FIFO to obtain the timestamp information for PTP software processing.

A FIFO status read can be omitted if the FIFO read delay is determined. CPU can read the RX FIFO without any delay while for TX FIFO, a delay is necessary and most often depends on the sum of MTU delay of a scheduled packet, DMA delays and the PTP packet transmit delays. In general, 3.MTU delay is the common value for TX FIFO read delay. Download and install Quartus II Subscription Edition software v14.1 and Altera Arria V SoC Development Kit Installations on your Windows host. Place two Arria V SoC development boards (5ASTFD5K3F40I3NES) side by side.

In the following steps, the two Arria V SoC development boards will be referred to as Board A and Board B. Setup the SMA connections between these 2 boards per below:. Port J24 on Board A connects to port J31 on Board B. Port J25 on Board A connects to port J32 on Board B.

Port J24 on Board B connects to port J31 on Board A. Port J25 on Board B connects to port J32 on Board A. Connect the micro SD card with the bootable image to J5 port on board A. Connect USB II blaster cable from Board A to your Windows host that has Arria V SoC development kit installed. Turn on the power for Board A to load the bootable image.

The Arria V 10GbE appears on the LCD screen on the board when the image is successfully loaded. Open the Clock Control application from the Arria V SoC development kit installation on your Windows host. Set Channel 0 reference clock source, Si570(X3) to 644.53125MHz. This step is required to run the reference design at 10Gbps data rate. FPGA LED 0 will blink every 2 seconds to indicate that the hardware clock is running at 10Gbps data rate if the reference clock source Si570 is successfully configured. Use ethtool -d eth0 to view MAC register settings.

You can use the Ptp4l software in the LinuxPTP package to measure the timestamp accuracy of the reference design. By default, the hardware timestamping is selected and time interval between SYNC messages is set to 1 second. Use testptp -c to view the PTP hardware clock capabilities on both boards.

Use ethtool -C eth0 tx-frames 1 command to send packet to the stack without any delay on both boards. This must be done before executing ptp4l command. Type ptp4l -i eth0 -m to start a PTP Master on Board A with the IP address of 10.0.0.1. Type ptp4l -i eth0 -m -s to start a PTP Client on Board B with the IP address of 10.0.0.2. The PTP measurement starts at this point. Stop the PTP measurement on Board B (PTP client) by pressing CTRL + C on your keyboard. Type testptp -f 0 to reset the MAC clock period default to 6.4ns on Board B (PTP client) after the measurement has stopped.

Optionally, type testptp -s to reset PTP hardware clock time to system time at PTP client. By default, the PTP Master sends 1 SYNC message per every second. You can create a configuration file to override the default settings of ptp4l.

The following code shows the example of ptp4l configuration file to set PTP Master to send 512 SYNC messages every second. This setting provides a timestamp accuracy of 6.99ns for every 100 samples. At times, you may need to modify the reference design according to your system requirements and recompile the reference design. You are required to regenerate the alteraeth10g1588refdesignmsgdmatop.qsys file for compilation. Following are the steps to guide you in regenerating the design files and replacing the RBF file into the system image. You are required to use Quartus II Subscription Edition v14.1 for these procedures. Download the alteth1588rd.qsys.zip file to your computer and unzip the folder.

Launch Quartus II software. In Quartus II software, click File - Open Project and browse to av1588top.qpf file to open the reference design project.

Once the the project file is open, click on Tools - Qsys in the Quartus II software. In the Qsys interface, click File - Open and browse to alteraeth10g1588refdesignmsgdmatop.qsys file to open the reference design Qsys file. Once the reference design Qsys file is opened, click Generate HDL.

Below are the modules available in the Altera 1588 system solution reference design:. A 1588 capable Ethernet MAC and PHY, capable of very precise time stamping of packets with ToD value and an indication on the time-stamp offset. This time stamping achieves equal accuracy in both 1-step and 2-step operations. A ToD clock module that supports loading of real ToD value and fine-grain update of its value and frequency. Clear-text packet parser that can be used to detect PTP packet types and then tell the Ethernet MAC the time-field offset for the following packet types: UDP over IPv4, UDP over IPv6, stacked VLAN. This block is made available in clear-text so that the user can easily augment the code to cover other packet types the users may need such as MPLS or MAC-in-MAC.

ToD synchronizer to synchronize different ToDs running in different clock domains; for example, in a system of network line cards to a system master ToD. These building blocks can be put together in a useful system combined with the user provided CPU and software stack to create a high-quality 1588 solution. It is the responsibility of the software stack, which the user either creates or obtains from a third-party, to implement the overall 1588 stack, including the corresponding logic to support different modes for synchronization process. The following diagram illustrates the hardware modules in this 1588 system reference design. Altera provides a Time of Day Clock (ToD) module to ease user's implementation when using Altera Ethernet MAC-based 1588 system.

The ToD module is a counter responsible for generating the current real time of day locally. A processor with a Timing Servo Control Software updates the ToD counter, typically via fine-grain adjustments in terms of phase and frequency corrections through relevant registers. The ToD can provide both a 64-bit time useful for the correction field used in a transparent clock (TC) and a full 96-bit time useful for ordinary clock (OC) and boundary clock (BC). You can instantiate a master ToD module to time-stamp the transmitted and received packets.

One ToD module can be shared across multiple MACs. You must enable the 64-bit timestamp when using TC, otherwise use 96-bit timestamp.You may use Altera Ethernet IEEE 1588 TOD Synchronizer to synchronize multiple slave ToDs to a single master ToD. Packet Parser. The Ethernet Packet Classifier functions as a packet parser module for Altera Ethernet MAC-based 1588 system. In the transmit direction, the Packet Parser module is used to determine the type of packet being sent, determine the appropriate location for the time stamp field and provide this information via a command to the 1588 MAC transmitter for further processing. The module is also able to provide the information of the timestamp offset and whether there is an update to the IPv6 UDP correction field.

In the receive direction, this block checks whether the local timestamp of the packet received on the Ethernet MAC receiver is indeed for a PTP packet. For example, the 1588 PTP packet’s timestamp field location relative to the Start Of Packet (SOP) is different for a PTP packet encapsulated over Ethernet versus for a PTP packet encapsulated over UDP over IPv6 over Ethernet. The Central Processing Unit (CPU). A FIFO is used to associate a PTP event with a timestamp for later retrieval. For example, in a 2-step operation, the FIFO will be used to remember the time that a packet has gone out so that it can be looked up and retrieved at the time that the CPU is ready to send out the follow-up response. Though the 1588 protocol is a slow protocol with 128 frames per second, the 1588 packets may arrive in burst or many contexts such as simultaneous flows or many PTP domains can coexist in a single clock device. Hence, a FIFO is sometimes required depending on the system performance requirements in a 2-step operation.

Similarly, in 1-step operation, the timestamp T3 and optionally T2 needs to be collected by the PTP stack through a FIFO. The use cases are an Ordinary Clock-Master in 2-step, Boundary Clock-Master in 2-step, Ordinary Clock-Slave in both 1-step and 2-step, Boundary Clock-Slave in both 1-step and 2-step & Transparent Clock (TC) in 2-step. A typical size of the FIFO required is a network parameter, which can approximately range from 64 to 256 entrees.

The FIFO stores the timestamp along with the signature of the packet for the CPU to read the timestamp later. The CPU can match the timestamp’s signature with its signature of the packet before accepting the timestamp. If the timestamp is read out of order, the CPU can keep a shadow copy of the entry to match with other signatures and read the FIFO for the packet in context. A FIFO works more efficiently than a CAM the timestamps are read in order. Clocking and Reset Scheme. PMA Registers Byte Offset Bit R/W Name 0x0088 RO pmatxpllislocked 0x0110 1 RW resettxdigital 2 RW resetrxanalog 3 RW resetrxdigital 0x0184 RW physerialloopback 0x0190 RW pmarxsetlocktodata 0x0194 RW pmarxsetlocktoref 0x0198 RO pmarxislockedtodata 0x019C RO pmarxislockedtoref 0x02A0 0 RW txinvpolarity 1 RW rxinvpolarity 2 RW rxbitreversalenable 3 RW rxbytereversalenable 4 RW forceelectricalidle 0x02A4 0 R rxsyncstatus 1 R rxpatterndetect 2 R rxrlv 3 R rxrmfifodatainserted 4 R rxrmfifodatadeleted 5 R rxdisperr 6 R rxerrdetect. Register Description and Address Offset for PTP Control Module Word Offset Bits Name Type Reset Value Description 0x00 1:0 txrxpktparserclockmode RW 2'b00 Specify the operating clock mode for PTP port.

2'b00: Ordinary Clock 2'b01: Boundary Clock 2'b10: End-to-end Transparent Clock 2'b11: Peer-to-peer Transparent Clock 8 txpktparsertwostepmode RW 1'b0 Specify the operation mode for the synchronization process. 1'b0: 1-step operation mode 1'b1: 2-step operation mode.

10 txpktparserpacketwithcrc RW 1'b0 Enable the packet parser to indicate whether the incoming packet to the MAC includes CRC. This register is required by TX packet parser to calculate the offset location for checksum corrector for UDP/IPv6 packets. 0x04 0 rxpktfltfwduserucastmatch RW 1'b0 Forward unicast packet that matched the MAC address to user logic. 1'b0: Allow unicast packet which matched the MAC address to be forwarded to user logic. 1'b1: Drop unicast packet that matched the MAC address.

1 rxpktfltfwduserucastxmatch RW 1'b1 Forward unicast packet that does not matched the MAC address to user logic. 1'b0: Drop unicast packet that do not match the MAC address. 1'b1: Allow unicast packet which does not match the MAC address to be forwarded to user logic.

2 rxpktfltfwdusermcast RW 1'b1 Forward multicast packet to user logic. 1'b0: Drop multicast packet. 1'b1: Allow multicast packet to be forwarded to user logic. 3 rxpktfltfwduserbcast RW 1'b1 Forward Broadcast packet to user logic. 1'b0: Drop broadcast packet. 1'b1: Allow broadcast packet to be forwarded to user logic.

8 rxpktfltfwdswucastmatch RW 1'b1 Forward unicast packet that matched the MAC address to software. 9 rxpktfltfwdswucastxmatch RW 1'b0 Forward unicast packet that does not matched the MAC address to software. 10 rxpktfltfwdswmcast RW 1'b1 Forward multicast packet to software. 11 rxpktfltfwdswbcast RW 1'b1 Forward Broadcast packet to software. 0x05 31:0 rxpktfltmacaddrprim31to0 RW 32'h0. 6-byte primary MAC address.

You must map the address to the registers in the following manner:. rxpktfltmacaddrprim31to0 = Last four bytes of the address. rxpktfltmacaddrprim47to32: First two bytes of the address 0x06 15:0 rxpktfltmacaddrprim47to32 RW 16'h0 0x20 0 txfifoclr RW 1'b0 Reset TX Egress TimeStamp FIFO. 1'b0: De-assert reset. 1'b1: Assert reset. 0x21 0 txfifotsfprintrdy RO 1'b0 Indicates the availability of the timestamp and the fingerprint. 1'b0: No timestamp and fingerprint available in the TX Egress Timsestamp FIFO.

1'b1: Timestamp and fingerprint available in the TX Egress Timestamp FIFO. 16:8 txfifousedwords RO 9'b0 Indicates the number of words in the FIFO.

0x25 31:0 txfiforecoveredtstamp31to0 RO 32'h0 The recovered timestamp. For 96-bit timestamp format, all TX FIFO recovered timestamp register-sets are used. For 64-bit timestamp format, only txfiforecoveredtstamp63to32 and txfiforecoveredtstamp31to0 registers are used. Read to txfiforecoveredtstamp95to64 register indicates the completion of a read transaction for timestamp and fingerprint registers.

Keith

Altera recommend to follow the below order to read the timestamp and fingerprint registers:. Read txfiforecoveredfprint31to0 register (optional).

Read txfiforecoveredtstamp31to0 register. Read txfiforecoveredtstamp63to32 register. Read txfiforecoveredtstamp95to64 register. 0x26 31:0 txfiforecoveredtstamp63to32 RO 32'h0 0x27 31:0 txfiforecoveredtstamp95to64 RO 32'h0 0x28 19:0 txfiforecoveredfprint31to0 RW 20'h0 The fingerprint corresponding to the timestamp. Read this register if the PTP stack is require to verify the timestamp correspond to the packet. 0x40 0 rxfifoclr RW 1'b0 Reset RX Ingress TimeStamp FIFO. 1'b0: De-assert reset.

Fwd: Keith's Image Stacker For Mac Os

1'b1: Assert reset. 0x41 0 rxfifotsfprintrdy RO 1'b0 Indicates the availability of the timestamp and the fingerprint. 1'b0: No timestamp and fingerprint available in the RX Ingres Timestamp FIFO. 1'b1: Timestamp and fingerprint available in the RX Ingress Timestamp FIFO. 16:8 rxfifousedwords RO 9'b0 Indicates the number of words in the FIFO. 0x45 31:0 rxfiforecoveredtstamp31to0 RO 32'h0 The recovered timestamp. For 96-bit timestamp format, all RX FIFO recovered timestamp register-sets are used.

For 64-bit timestamp format, only rxfiforecoveredtstamp63to32 and rxfiforecoveredtstamp31to0 registers are used. Read to rxfiforecoveredtstamp95to64 register indicates the completion of a read transaction for timestamp and fingerprint registers. Altera recommend to follow the below order to read the timestamp and fingerprint registers:.

Read rxfiforecoveredfprint31to0 register (optional). Read rxfiforecoveredtstamp31to0 register. Read rxfiforecoveredtstamp63to32 register.

Read Rxfiforecoveredtstamp95to64 register. 0x46 31:0 rxfiforecoveredtstamp63to32 RO 32'h0 0x47 31:0 rxfiforecoveredtstamp95to64 RO 32'h0 0x48 19:0 rxfiforecoveredfprint31to0 RW 20'h0 The fingerprint corresponding to the timestamp. Read this register if the PTP stack is require to verify the timestamp correspond to the packet. 1588 ToD Clock Registers.

Register Description and Address Offset for 1588 TOD Clock Byte Offset R/W Name Description HW Reset 0x0000 RW SecondsH. Bits 0 to 15: High-order 16-bit second field. Bits 16 to 31: Not used.

0x0 0x0004 RW SecondsL Bits 0 to 32: Low-order 32-bit second field. 0x0 0x0008 RW NanoSec Bits 0 to 32: 32-bit nanosecond field. 0x0 0x0010 RW Period. Bits 0 to 15: Period in fractional nanosecond. Bits 16 to 19: Period in nanosecond.

Bits 20 to 31: Not used. N 0x0014 RW AdjustPeriod The period for the offset adjustment. Bits 0 to 15: Period in fractional nanosecond. Bits 16 to 19: Period in nanosecond. Bits 20 to 31: Not used. 0x0 0x0018 RW AdjustCount. Bits 0 to 19: The number of AdjustPeriod clock cycles used during offset adjustment.

Bits 20 to 31: Not used. 0x0 0x001C RW DriftAdjust The drift of ToD adjusted periodically by adding a correction value as configured in this register space. Bits 0 to 15: Adjustment value in fractional nanosecond (DRIFTADJUSTFNS). This value is added into the current ToD during the adjustment.

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Bits 16 to 19: Adjustment value in nanosecond (DRIFTADJUSTNS). This value is added into the current ToD during the adjustment. Bits 20 to 32: Not used. 0x0 0x0020 RW DriftAdjustRate The count of clock cycles for each ToD’s drift adjustment to take effect. Bits 0 to 15: The number of clock cycles (ADJUSTRATE). The ToD adjustment happens once after every period in number of clock cycles as indicated by this register space.

Fwd: Keith's Image Stacker For Mac Pro

Bits 20 to 32: Not used. 0x0 Interface Signals.

Clock and Reset Interface Signals Signal Direction Width Description resetresetn input 1 Reset signal for the system reference design. This is asynchronous and active low signal. Fpgaclk100 input 1 Arria V SoC operating clock.

Refclk6440 input 1 Reference clock for Altera 10GBASE-R PHY for channel 0. Refclk6441 input 1 Reference clock for Altera 10GBASE-R PHY for channel 1. Clk644out output 1 Reference clock for Altera 10GBASE-R PHY output signal for debug purposes. PHY Interface Signals. Arria V HPS Interface Signals Signal Direction Width Description HPS DDR3 SDRAM hpsmemorymema Output 15 Address bus. Hpsmemorymemba Output 3 Bank address.

Hpsmemorymemck memckn Output 1 Memory clock. Memcke Output 1 Clock enable. Memcsn Output 1 Chip select.

Memrasn Output 1 Row address strobe. Memcasn Output 1 Column address strobe. Memwen Output 1 Write enable. Memresetn Output 1 Reset memdq Bidirectional 40 Data.

Memdqs Bidirectional 5 Data strobe. Memdqsn Bidirectional 5 Data strobe. Memodt Output 1 On-die termination.

Memdm Output 5 Data mask. Octrzqin Input 1 OCT reference resistor pins for RZQ. HPS Peripheral hpsuart0TX Output 1 Output signal for UART channel 0. This signal is required for serial console communication to host. Hpsuart0RX Input 1 Input signal for UART channel 0. This signal is required for serial console communication to host.